1. Field of the Invention
This invention is in the field of integrated circuits, and is specifically directed to the method of forming trench isolation.
2. Description of the Related Art
As the demand for more complex functions and higher performance in integrated circuits increases, it becomes necessary to pack active devices more densely. Density depends upon the area required to isolate transistors from one another as well as upon the active area of transistors. One conventional method of isolation is the well-known local oxidation [LOCOS] technique in which transistors are separated via a locally grown field oxide. According to this technology, the degree of isolation depends on the length and depth of the field oxide separating the transistors. By increasing either the length or the depth of the field oxide, the length of the leakage path between the two active areas is also increased. However, to increase circuit density, the length of the separating field oxide must also be minimized. Increasing the depth of the field oxide has the side effect of encroachment into the active areas of the neighboring transistors. This encroachment results in the deformation phenomenon known as `bird's beak`.
A second method of isolation, in CMOS processes, uses junction isolation. A P-channel transistor can be isolated from a N-channel transistor by biasing the n-well positive with respect to the p-well, thereby reverse-biasing the junction therebetween. In addition, two N-channel transistors may be isolated from each other by placing a p-well between the two N-channel transistors. There are, however, drawbacks to such junction isolation. One drawback is that additional surface area is required by the junction isolation, causing a less efficient use of space. Another drawback is that junction isolation adds parasitic capacitance to the integrated circuit.
A modern method of isolation uses an isolation trench. An example of an isolation trench is described in U.S. Pat. No. 4,631,803, issued on Dec. 20, 1986 and assigned to Texas Instruments Incorporated. This example uses a sidewall dielectric on the sidewalls of the trench, with a polysilicon plug filling the trench. The trench also has a thin oxide which covers the polysilicon plug. By using a polysilicon plug rather than an oxide filler, stress associated with the formation of an oxide filler as well as stress due to dissimilarities in the coefficients of thermal expansion of the substrate to the filler are reduced. Subsequent processing steps, however, may damage the thin oxide covering the trench causing leakage into the trench. Such leakage can result from, for example, the overetching of contact vias. For this reason contacts made directly over the trench are therefore generally prohibited, resulting in a less efficient use of space and reduced density.
A second example of an isolation trench is described in U.S. Pat. No. 4,835,115, issued May 30, 1989 and also assigned to Texas Instruments Incorporated. This example uses a thick oxide cap grown over a polysilicon plug to allow subsequent metal-to-metal and metal-to-poly contacts to be made directly over the trench. The thick oxide cap minimizes the risk of overetching the contact vias which would otherwise result in leakage from an overlying layer into the trench. Growing a thick oxide can, however, result in the formation of voids in the topology of the trench and surrounding area.
It is therefore an object of this invention to provide a method for fabricating a trench in a semiconductor body which reduces the topography of the trench.
It is further an object of this invention to provide such a method which also allows for contacts to be made directly over the trench.
It is still further an object of this invention to provide such a method which makes efficient use of surface area of the integrated circuit.
It is still further an object of this invention to provide such a method which may be utilized in bipolar, MOS and BiCMOS processes.
Other objects and advantages of this invention will be apparent to those of ordinary skill in the art having reference to the following specification in conjunction with the drawings.